Condensed router headers with low latency output port calculation
US8572353B1 · kind B1 · utility
38Cited by
4References
26Claims
0Family size
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Key dates
| Filing date | Sep 20, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jan 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from an origin core to a destination core over a route including multiple cores; and at each core in the route before the destination core, routing the packet to the next core in the route according to a respective symbol in a sequence of multiple symbols. The respective symbol has a first symbol value indicating a single likely direction and the respective symbol has a second symbol value indicating multiple less likely directions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.