Computing device and method for managing motherboard test
US8572436B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 25, 2011 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Jun 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for managing a test of a motherboard can create a first test data consisting of test items. In the first test data, one or more selected test items to perform can be identified. A second test data is obtained by performing a logical NOR operation on the test bits corresponding to the selected test items. After performing the test items, a third test data is created by setting the test bits corresponding to the selected test items that pass the test to the test bits of the selected test items in the first test data, and by setting the test bits corresponding to the selected test items that fail the test to the test bits of the test items that have not been selected in the first test data. By comparing the third with the test data, a test result of the motherboard is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.