Reconfigurable logic block
US8572538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2012 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Feb 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17758
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.