Inter-thread data communications in a computer processor
US8572628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2010 |
| Grant date | Oct 29, 2013 |
| Priority date | — |
| Expiry date | Dec 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/546
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Inter-thread data communications in a computer processor with multiple hardware threads of execution, each hardware thread operatively coupled for communications through an inter-thread communications controller, where inter-thread communications is carried out by the inter-thread communications controller and includes: registering, responsive to one or more RECEIVE opcodes, one or more receiving threads executing the RECEIVE opcodes; receiving, from a SEND opcode of a sending thread, specifications of a number of derived messages to be sent to receiving threads and a base value; generating the derived messages, incrementing the base value once for each registered receiving thread so that each derived message includes a single integer as a separate increment of the base value; sending, to each registered receiving thread, a derived message; and returning, to the sending thread, an actual number of derived messages received by receiving threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.