Method of manufacturing a semiconductor device
US8574974B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2012 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Dec 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.