Buffer system having reduced threshold current
US8575963B2 · kind B2 · utility
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19References
11Claims
0Family size
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Inventor
Key dates
| Filing date | Mar 23, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Mar 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.