Frequency synthesizer with zero deterministic jitter
US8575973B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2012 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | May 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B2202/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.