Cascaded class D amplifier with improved linearity
US8576003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2012 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Apr 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/2173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier includes first and second stages. The first stage includes an input node for receiving an analog input signal, an analog digital converter for converting the analog input signal to a digital input signal, and a first switching circuit for outputting a first analog intermediate output signal in response to receiving a digital pulse width modulated signal that is based on the digital input signal. The second stage is configured to receive a pulse width modulation quantization error of the first stage, scale the pulse width modulation quantization error of the first stage by a gain factor to produce a scaled pulse width modulation quantization error of the first stage, and output a second analog intermediate output signal based on the scaled pulse width modulation quantization error of the first stage. A summation circuit combines the first and second analog intermediate output signals to generate an amplified output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.