Display device
US8576214B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 19, 2010 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Feb 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0297
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.