Memory with regulated ground nodes
US8576611B2 · kind B2 · utility
5Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2010 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Jun 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.