Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor

US8576614B2 · kind B2 · utility

Assignees

• IMEC · BE
• Katholieke Universiteit Leuven, KU LEUVEN R&D · BE

Inventors

• Marc Heyns · Linden, BE
• Cedric Huyghebaert · Heverlee, BE
• Anne S. Verhulst · Houtvenne, BE
• Daniele Leonelli · Leuven, BE
• Rita Rooyackers · Kessel-Lo, BE
• Wim Dehaene · Kessel-Lo, BE

Key dates

• Filing date: Aug 16, 2012
• Grant date: Nov 5, 2013
• Expiry date: Aug 16, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/117
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.