Method of using multiplexing circuit for high speed, low leakage, column-multiplexing memory devices
US8576642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2013 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Apr 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.