Combined binary/decimal fixed-point multiplier and method
US8577952B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Oct 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4915
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.