Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode

US8578138B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mahesh S. Natu · Folsom, US
• Thanunathan Rangarajan · Savanuru, IN
• Gautam Doshi · Sunnyvale, US
• Shammanna M. Datta · Hillsboro, US
• Baskaran Ganesan · Bengaluru, IN
• Mohan J. Kumar · Beaverton, US
• Rajesh S. Parthasarathy · Hillsboro, US
• Frank Binns · Portland, US
• Rajesh Nagaraja Murthy · Bengaluru, IN
• Robert C. Swanson · Olympia, US

Key dates

• Filing date: Aug 31, 2009
• Grant date: Nov 5, 2013
• Expiry date: Jun 2, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3017
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.