SerDes power throttling as a function of detected error rate
US8578222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2011 |
| Grant date | Nov 5, 2013 |
| Priority date | — |
| Expiry date | Jan 1, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.