Memory arrays using nanotube articles with reprogrammable resistance
US8580586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2009 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Sep 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.