Metal oxide semiconductor transistor and method of manufacturing the same
US8580625B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jul 22, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Mar 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.