Method of patterning a semiconductor device having improved spacing and shape control and a semiconductor device
US8580637B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Feb 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.