Semiconductor device including chip with complementary I/O cells
US8581302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Dec 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.