Synchronous state machine with an aperiodic clock
US8581629B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2012 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | May 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1582
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.