Sample-and-hold circuit arrangement
US8581636B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 24, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Dec 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Sample-and-hold circuits typically operate at maximum speed when the sampling phase is much shorter than the holding phase. Thus, a device driving the sampling capacitor is disconnected most of the time. Methods and apparatus use the holding phase to store the full charge required by the sampling capacitor to track the amplifier output in at least two “boost” capacitors configured such that when the sampling capacitor is switched to the driver, the boost capacitors are also switched to the driver. Thus, the sampling capacitor is almost instantly charged to the required voltage, and the driver needs to supply only any remaining “error” charge, avoiding delays due to driver output slewing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.