Phase-lock loop-based clocking system, methods and apparatus
US8581643B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Oct 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In part, the invention relates to an optical coherence tomography system that includes one or more phased-locked loop circuits. In one embodiment, the phased-locked loop circuit includes a phase detector, a loop filter, and a voltage controlled oscillator wherein the phased-locked loop circuit is configured to generate a sample clock. The optical coherence tomography system can include an analog to digital converter having a sample clock input, an interferometric signal input, and a sample data output, the analog to digital converter configured to receive the sample clock and sample OCT data in response thereto. In one embodiment, the phased-locked loop circuit is configured to lock on a first signal in less than or equal to about 1 microseconds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.