Methods and apparatus for performing code correction for hybrid analog-to-digital converters in imaging devices
US8581761B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2012 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Oct 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Electronic devices may include image sensors having image sensor pixels. The pixels may be coupled to analog to digital converter (ADC) circuitry. The ADC may include a hybrid successive approximation register (SAR) ADC and ramp-compare ADC. The ramp-compare ADC may be controlled by count bits. The hybrid ADC may be subject to non-idealities at the transition between data conversion using the SAR ADC and the ramp-compare ADC. A voltage offset may be injected to the ramp-compare ADC to compensate for voltage glitches. The ramp-compare ADC may have an output range that is insufficiently matched to a least significant bit of the SAR ADC. An error correction bit may be added to the count bits to increase the output range of the ramp-compare ADC to match the SAR least significant bit. The ramp-compare ADC may include gain control circuitry to further match the output range to the SAR least significant bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.