Patent · US Active

Dynamic subroutine linkage optimizing shader performance

US8581912B2 · kind B2 · utility

4Cited by

10References

16Claims

0Family size

Assignee

Microsoft Corporation · US

Inventors

Michael V. Oneppo · Seattle, US
Craig Peeper · Kirkland, US
Andrew L. Bliss · Bellevue, US
John Lee Rapp · Seattle, US
Mark M. Lacey · Seattle, US

Key dates

Filing date	Jun 27, 2008
Grant date	Nov 12, 2013
Priority date	—
Expiry date	Sep 7, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06T2200/28
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.