Image processing circuit and associated method
US8582665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2009 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Oct 8, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/43
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image processing circuit includes a compression circuit, a plurality of first line buffers, a decompression circuit, and a motion estimation/compensation circuit. The compression circuit receives source image data and compresses the received source image data to generate a compressed image data. The first line buffers, coupled to the compression circuit, sequentially receive the compressed image data and buffer the compressed image data. The decompression circuit, coupled to the first line buffers, decompresses the compressed image data to generate a decompressed image data. The motion estimation/compression circuit, coupled to the decompression circuit, performs motion estimation/compensation according to the decompressed image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.