Method and apparatus for data quantization and packing with variable bit width and period
US8582696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2012 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Feb 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/067
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The various embodiments provide circuitry and methods for packing Log Likelihood Ratio (“LLR”) values into a buffer memory in a compressed format which reduces the amount of buffer memory required. Various embodiments use a type of quantization which reduces the bit width of the LLR values that are stored, with the particular level of quantization depending upon the code rate of the data. The degree, pattern, and periodicity of bit width compression employed may depend upon the code rate of the received transmission. Bit width patterns use for LLR value quantization may be generated by a shift register circuit which provides an efficient mechanism for controlling an LLR packer circuit based upon the code rate of the received signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.