Field-programmable gate array based accelerator system
US8583569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Dec 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/334
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and flexibility. The accelerator system may be used to implement a relevance-ranking algorithm, such as RankBoost, for a training process. The algorithm and related data structures may be organized to enable streaming data access and, thus, increase the training speed. The data may be compressed to enable the system and method to be operable with larger data sets. At least a portion of the approximated RankBoost algorithm may be implemented as a single instruction multiple data streams (SIMD) architecture with multiple processing engines (PEs) in the FPGA. Thus, large data sets can be loaded on memories associated with an FPGA to increase the speed of the relevance ranking algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.