Hierarchy management method and system for HARQ memory
US8583976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2010 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Oct 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1812
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention provides a method for hierarchy management for a HARQ memory, wherein, the HARQ memory includes an on-chip memory including one or more storage blocks, each of which corresponds to a using status bit for indicating whether the storage block is overlayable. The method includes the following steps of: when receiving new data of a coded block, searching the on-chip memory for any overlayable storage block, and if there exists an overlayable storage block, storing the new data into the storage block and setting the using status bit corresponding to the storage block to be un-overlayable; if there is no overlayable storage block, storing the new data into an off-chip memory; and when the new data are checked and pass the check, setting the using status bit corresponding to the storage block in which the new data are stored to be overlayable. The invention also provides a corresponding system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.