Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
US8584072B1 · kind B1 · utility
8Cited by
15References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 31, 2012 |
| Grant date | Nov 12, 2013 |
| Priority date | — |
| Expiry date | Aug 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.