Process for fabricating semiconductor devices and a semiconductor device comprising a chip with through-vias
US8586450B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2011 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jan 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first wafer having at least one first integrated-circuit chip and a first support layer surrounding the first integrated circuit chip. A first electrical-connection layer is placed on a frontside of the first wafer and includes a first electrical-connection network. A second wafer is placed on a frontside of the first electrical-connection layer. The second wafer includes at least one second integrated-circuit chip and a second support layer surrounding the second integrate circuit chip. The second integrated circuit chip has an active side facing the first electrical-connection layer, and one or more through-holes filled with a conductor forming electrical-connection vias. A second electrical-connection layer is placed on the backside of the second wafer and includes a second electrical-connection network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.