Semiconductor package structure
US8587013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Nov 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/841
Abstract
A semiconductor package structure includes an insulating substrate, a patterned conductive layer, a light emitting diode (LED) chip and a conductive connection part. The insulating substrate has an upper surface divided into an element configuration region and an element bonding region. The patterned conductive layer includes plural circuits located in the element configuration region and at least one bonding pad located in the element bonding region. The LED chip is flip chip bonded on the patterned conductive layer and electrically connected to the circuits. The conductive connection part has a first end point electrically connected to the bonding pad and a second end point electrically connected to an external circuit. The bonding pad and a corner of the LED chip are disposed correspondingly. A horizontal distance between an apex of the corner and the first end point of the conductive connection part is greater than or equal to 30 micrometers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.