Dual-gate normally-off nitride transistors
US8587031B2 · kind B2 · utility
12Cited by
8References
21Claims
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Key dates
| Filing date | Jul 25, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jul 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.