Low power multi-core decoder system and method
US8587595B2 · kind B2 · utility
569Cited by
286References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2009 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Feb 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/06037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A portable data terminal including a multi-core processor having at least a first core and a second core, at least one illumination assembly and at least one imaging assembly and data storage means configured to store a plurality of program instructions, the program instructions including at least one one-dimensional decoder and at least one two-dimensional decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.