Memory element, stacking, memory matrix and method for operation

US8587988B2 · kind B2 · utility

Assignees

• Forschungszentrum Jülich GmbH · DE
• Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen · DE

Inventors

• Eike Linn · Würselen, DE
• Carsten KUEGELER · Lippstadt, DE
• Roland ROSEZIN · Bernau, DE
• Rainer Waser · Aachen, DE

Key dates

• Filing date: May 8, 2010
• Grant date: Nov 19, 2013
• Expiry date: May 31, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/177
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.