Systems and methods for managing cache destage scan times
US8589623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jun 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.