Cache memory device, processor, and processing method
US8589636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2010 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Mar 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.