Dynamically configurable memory system
US8589650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Nov 11, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a digital system with a processor coupled to a paged memory system, the memory system may be dynamically configured using a memory compaction manager in order to allow portions of the memory to be placed in a low power mode. As applications are executed by the processor, program instructions are copied from a non-volatile memory coupled to the processor into pages of the paged memory system under control of an operating system. Pages in the paged memory system that are not being used by the processor are periodically identified. The paged memory system is compacted by copying pages that are being used by the processor from a second region of the paged memory into a first region of the paged memory. The second region may be placed in a low power mode when it contains no pages that are being used by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.