Instruction set architecture extensions for performing power versus performance tradeoffs
US8589665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2010 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jun 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.