Patent · US Active

Verifying correctness of processor transactions

US8589734B2 · kind B2 · utility

3Cited by

5References

27Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Allon Adir · Kiryat Tivon, IL
John Martin Ludden · Butlers Corners, US
Avi Ziv · Haifa, IL

Key dates

Filing date	Aug 26, 2010
Grant date	Nov 19, 2013
Priority date	—
Expiry date	Dec 21, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F2115/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.