Using direct memory access to initialize a programmable logic device
US8589834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2012 |
| Grant date | Nov 19, 2013 |
| Priority date | — |
| Expiry date | Jul 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17758
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment includes an integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD. The IC includes an input/output (I/O) interface and a PLD interface. The I/O interface converts a signal format between the IC and the PLD. The PLD interface includes a configuration and status register, a data buffer, and pacing logic. The configuration and status register is adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface. The data buffer temporarily holds PLD programming data received from a DMA control at a DMA speed. The pacing logic controls the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.