Patent · US Active

Architectural support for automated assertion checking

US8589895B2 · kind B2 · utility

0Cited by
6References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 13, 2010
Grant dateNov 19, 2013
Priority date
Expiry dateSep 19, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F11/3692
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.