Method of forming low resistance gate for power MOSFET applications

US8592277B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• Sreevatsa Sreekantham · West Jordan, US
• Ihsiu Ho · Salt Lake City, US
• Fred Session · Sandy, US
• James Kent Naylor · Kaysville, US

Key dates

• Filing date: Sep 27, 2010
• Grant date: Nov 26, 2013
• Expiry date: May 16, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/685

Abstract

A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.