Stacked NMOS DC-to-DC power conversion
US8593128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Jul 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0081
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Another embodiment includes a voltage regulator. The voltage regulator includes a series switch element connected between a first voltage supply and a common node, the series switch element comprising an NMOS series switching transistor, a shunt switch element connected between the common node and a second voltage supply, the shunt switch element comprising an NMOS shunt switching transistor. The voltage regulator further includes means for closing the series switch element during a first period by applying a switching gate voltage to a gate of the NMOS series switch transistor of the series switch element, wherein the switching gate voltage has a voltage potential of at least a threshold voltage greater than a voltage potential of the common node, means for closing the shunt switch element during a second period, the shunt switch element comprising an NMOS shunt switching transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.