Method and device for testing TSVS in a 3D chip stack
US8593170B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2010 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Dec 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06596
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.