High signal level compliant input/output circuits
US8593203B2 · kind B2 · utility
7Cited by
54References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Aug 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.