Semiconductor device, information processing system including same, and controller for controlling semiconductor device
US8593899B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2011 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Oct 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with a column command, a memory cell selected by the row address and column address in a bank selected by the bank address included in a core chip selected by the chip address is accessed. This can increase the number of banks recognizable to a controller, thereby improving the memory access efficiency of the semiconductor device which includes the plurality of memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.