Digital signal processor with adjustable data rate and methods thereof
US8594168B2 · kind B2 · utility
3Cited by
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8Claims
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Inventors
Key dates
| Filing date | Feb 29, 2012 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Feb 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0007
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
As a digitized representation of an intermediate frequency television signal moves through a demodulator it undergoes a number of processes, including conversion from an analog signal to a digitized data, digital signal processing of the digitized data, and the like. The rate at which the digitized data moves through the digital signal processor of the demodulator for processing is referred to as the data rate of the DSP. The demodulator can vary the data rate based on a selected television channel, thereby reducing the level of interference at the demodulator resulting from noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.