Jitter compensation
US8594253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2008 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | May 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods for jitter compensation in a receiver system are useful to improve performance. One such circuit includes a combiner block for combining a reference signal with an input signal (Sin) of the circuit, and a converter stage for converting the input signal (Sin) together with the reference signal. The converter stage is clocked by a clock signal modulated by a jitter signal. A forward path having a first mixer unit is provided for multiplying a copy of an output signal (A) of the converter stage with the frequency of the reference signal in order to generate a jitter compensating signal (B). A compensation unit for compensating jitter in the output signal (A) of the converter stage in a direct output path with the jitter compensating signal (B) is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.