Distributed performance counters
US8595389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2010 |
| Grant date | Nov 26, 2013 |
| Priority date | — |
| Expiry date | Oct 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2117
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.