Patent · US Active

Dynamic arbitration schemes for multi-master memory systems

US8595402B1 · kind B1 · utility

2Cited by

11References

20Claims

0Family size

Assignee

Marvell International Ltd. · BM

Inventors

Uri Erlich · Matan, IL
Udi Shtalrid · Beer Yaakov, IL

Key dates

Filing date	Mar 2, 2011
Grant date	Nov 26, 2013
Priority date	—
Expiry date	Jan 25, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/1652
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Apparatus includes a plurality of ports and arbitration circuitry. The plurality of ports is configured to connect a memory to a respective plurality of processing units that are configured to access the memory. The arbitration circuitry is configured to grant the processing units access to the memory via the ports in accordance with an arbitration scheme including multiple, alternating priority periods, such that in each priority period a respective processing unit is assigned an absolute priority over others of the processing units and the others of the processing units are assigned predefined relative priorities over one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.